MODEL OF ADAPTIVE ERROR CORRECTION SYSTEM IN COMPUTER SYSTEMS
DOI:
https://doi.org/10.35546/kntu2078-4481.2026.1.49Keywords:
adaptive error correction, computer systems, energy efficiency, LDPC, FPGA, wireless sensor networksAbstract
The paper examines the issues of ensuring an appropriate level of reliability and integrity of data transmission within modern distributed computer systems. The main focus is on heterogeneous Internet of Things (IoT) networks, extensive Wireless Sensor Networks (WSN), and Edge Computing systems operating in complex electromagnetic environments. The subject of the study includes methods, algorithms, and architectural models of adaptive error correction, which allow for dynamic modification of hardware coding parameters in real-time. The adaptation process is implemented based on a multidimensional vector of factors, including the current state of the communication channel (noise level, interference, fading), available energy resources of the autonomous device (charge level, source status), and applicationlayer requirements regarding permissible latency and throughput. It has been established that under conditions of strict power consumption constraints and operation in a stochastic environment, the use of traditional static coding methods leads to irrational use of hardware resources. This phenomenon manifests as a dichotomy of inefficiency: either excessive energy consumption for complex computational operations under favorable transmission conditions or critical data loss due to sudden noise bursts, the correction of which exceeds the capabilities of a fixed code. The paper proposes an FPGA-oriented system model based on the principles of algorithmic switching between different coding modes: from «transparency» modes (no coding) and the use of simple Hamming codes to the application of powerful iterative Low-Density Parity-Check (LDPC) codes. The developed model incorporates a complex multi-criteria decision-making approach covering Signal-to-Noise Ratio (SNR) estimation, battery discharge gradient monitoring, and Quality of Service (QoS) requirements, particularly permissible delay indicators. Theoretical justification of the effectiveness of the proposed adaptive approach is presented. Particular emphasis is placed on the feasibility of using FPGA architecture, which enables hardware acceleration of ether analysis processes and instantaneous reconfiguration of computational blocks. Analytical estimates indicate that such implementation will allow reducing the dynamic power consumption of the digital part of the system and ensuring stable adherence to the specified reliability level across a wide range of operating conditions.
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